4-29 October 2021

All-VIRTUAL conference

Welcome to IIRW

The IEEE International Integrated Reliability Workshop (IIRW) originated from the Wafer Level Reliability Workshop in 1982. The IIRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

Tutorials, paper presentations, poster sessions, moderated discussion groups, special interest groups, and the informal format of the technical program provide a unique environment for understanding, developing, and sharing reliability technology and test methodologies for present and future semiconductor applications as well as ample opportunity for open discussions and interactions with colleagues.

Due to the situation with the COVID-19, the conference will be held as ALL-VIRTUAL.

IIRW 2020 Best student paper

"Circuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks" by Tommaso Zanotti, Francesco Maria Puglisi and Paolo Pavan


The IIRW technical program and management committee invites abstracts related to the many areas of semiconductor reliability, such as:

  • Plasma induced damage (PID)

  • FEOL/MOL/BEOL dielectrics (high-k, SiO 2 , SiON, low-k)

  • FET, FinFET, SOI, III-V, SiGe reliability (HC, BTI, TDDB, etc.)

  • Conventional and emerging memories (Flash, RRAM, etc.)

  • Neuromorphic devices and circuits reliability

  • Emerging technologies and devices (2D materials, IGZO, etc.)

  • Power, wide-bandgap (SiC, GaN, etc.) devices reliability

  • RF and mm/sub-mm Wave devices reliability

  • Modeling and simulation of reliability, including self-heating

  • Failure analysis and Advanced packaging reliability

  • Impact of devices degradation on circuit reliability

  • Design in reliability (products, circuits, systems, processes)

  • Advanced automotive circuits, systems, products reliability

  • Customer/manufacturer product reliability requirements

  • Wafer-level reliability tests for monitoring and qualification

Important Dates

Regular Abstract Extended Deadline: July 30, 2021

Late News Deadline: September 10, 2021

Registration Fees

IEEE Member: $200

Non-IEEE Member: $250


General Chair: Matthew Ring gc.iirw@gmail.com

Technical Program Chair: Matthew Hogan tpc.iirw@gmail.com